The invention relates to a memory system, in particular a buffered memory system, e.g., a fully buffered memory system, a method for operating a memory system, and a device for use with a memory system.
In the case of conventional memory devices, in particular conventional semiconductor memory devices, one differentiates between functional memory devices (e.g., PLAs, PALs, etc.), and table memory devices, e.g., ROM devices (ROM=Read Only Memory—in particular PROMs, EPROMs, EEPROMs, flash memories, etc.), and RAM devices (RAM=Random Access Memory—in particular e.g., DRAMs and SRAMs).
A RAM device is a memory for storing data under a predetermined address and for reading out the data under this address later. In the case of SRAMs (SRAM=Static Random Access Memory), the individual memory cells consist e.g., of few, for instance 6, transistors, and in the case of DRAMs (DRAM=Dynamic Random Access Memory) in general only of one single, correspondingly controlled capacitive element.
In many applications, several DRAMs are arranged on a single, separate memory module, e.g., a separate memory card. Further, several of such memory modules—each having several DRAMs—may be connected to a respective microprocessor or memory controller via a bus system. However, the higher the number of memory modules/DRAMs connected to the microprocessor/memory controller, and the higher the data rate, the worse the quality of the signals exchanged between the memory modules/DRAMs, and the microprocessor/memory controller.
For this reason, “buffered” memory modules are used, e.g., registered DIMMs. Buffered memory modules include—in addition to several DRAMs—one or several buffer components, receiving the signals from the microprocessor/memory controller, and relaying them to the respective DRAM (and vice versa). Hence, the respective memory controller only needs to drive one capacitive load per DIMM on the bus.
To further enhance the data rate, and/or the number of memory modules which may be connected to a respective microprocessor/memory controller, FBDIMMs (Fully Buffered DIMMs) are used.
FIG. 1 illustrates a memory system 1 with FBDIMMs 2a, 2b, 2c (Fully Buffered DIMMs). In the memory system 1 illustrated in FIG. 1, up to eight memory cards/FBDIMMs 2a, 2b, 2c per channel may be connected to a microprocessor/memory controller 4. Each FBDIMM 2a, 2b, 2c includes a buffer component 5a, 5b, 5c, and several DRAMs 3a, 3b, 3c (for sake of simplicity, in FIG. 1 only one DRAM per memory card/FBDIMM 2a, 2b, 2c is illustrated). The FBDIMMs 2a, 2b, 2c may e.g., be plugged into corresponding sockets of a motherboard, which e.g., also includes the above microprocessor/memory controller 4.
As is illustrated in FIG. 1, the microprocessor/memory controller 4 may be connected to a first FBDIMM 2a of the FBDIMMs 2a, 2b, 2c via a first bus 6a, having a first channel (“South-bound channel” (SB channel)), and a second channel (“north-bound channel” (NB channel)). The SB channel of the bus 6a is used to send respective address, command, and data signals from the microprocessor/memory controller 4 to the buffer component 5a of the first FBDIMM 2a. Correspondingly similar, the NB channel of the bus 6a is used to send respective signals from the buffer component 5a of the first FBDIMM 2a to the microprocessor/memory controller 4.
As is further illustrated in FIG. 1, the first FBDIMM 2a of the FBDIMMs 2a, 2b, 2c is connected to a second FBDIMM 2b of the FBDIMMs 2a, 2b, 2c via a second bus 6b, which just as the bus 6a includes a first channel (“south-bound channel” (SB channel)), and a second channel (“north-bound channel” (NB channel)), and the second FBDIMM 2b of the FBDIMMs 2a, 2b, 2c is connected to a third FBDIMM via a third bus 6c (also having a first channel (“south-bound channel” (SB channel)), and a second channel (“north-bound channel” (NB channel)), etc., etc.
The FBDIMMs 2a, 2b, 2c work according to the “daisy chain” principle. The buffer component 5a of the first FBDIMM 2a of the FBDIMMs 2a, 2b, 2c relays the respective address, command, and data signals received via the “south-bound channel” of the first bus 6a from the microprocessor/memory controller 4—where required after a respective re-generation—via the “south-bound channel” of the second bus 6b to the buffer component 5b of the second FBDIMM 2b. Correspondingly similar, the buffer component 5b of the second FBDIMM 2b of the FBDIMMs 2a, 2b, 2c relays the respective address, command, and data signals received via the “south-bound channel” of the second bus 6b from the first FBDIMM 2a—where required after a respective re-generation—via the “south-bound channel” of the third bus 6c to the buffer component 5c of the third FBDIMM 2c, etc., etc.
Correspondingly inversely, the buffer component 5b of the second FBDIMM 2b of the FBDIMMs 2a, 2b, 2c relays the respective signals received via the “north-bound channel” of the third bus 6c from the above third FBDIMM—where required after a respective re-generation—via the “north-bound channel” of the second bus 6b to the buffer component 5a of the first FBDIMM 2a, and the buffer component 5a of the first FBDIMM 2a of the FBDIMMs 2a, 2b, 2c relays the respective signals received via the “north-bound channel” of the second bus 6b from the above second FBDIMM 2b—where required after a respective re-generation—via the “north-bound channel” of the first bus 6a to the microprocessor/memory controller 4.
As is further illustrated in FIG. 1, each DRAM 3a, 3b, 3c is connected to the corresponding buffer component 5a, 5b, 5c via a bus 7a, 7b, 7c, e.g., a respective stub-bus.
Each buffer component 5a, 5b, 5c knows its position in the above daisy chain. Which of the FBDIMMs 2a, 2b, 2c is being accessed at a certain time by the memory controller 4 may e.g., be determined in the respective buffer component 5a, 5b, 5c by comparing memory module identification data stored there (e.g., an “ID number”) with identification data sent by the memory controller 4 via the above buses 6a, 6b, 6c. In conventional systems 1, only one of the FBDIMMs 2a, 2b, 2c may be accessed at a certain time, i.e., no parallel access of FBDIMMs is possible.
The buffer component 5a, 5b, 5c of an accessed FBDIMM 2a, 2b, 2c does not only relay the received address, command, and data signals via a respective south-bound channel of one of the buses 6a, 6b, 6c to the next buffer component in the daisy chain (as explained above), but also relays the signals (where appropriate, in converted form) via the above stub-bus 7a, 7b, 7c to the DRAMs 3a, 3b, 3c provided on the accessed FBDIMM 2a, 2b, 2c. Further, signals received by a respective buffer component 5a, 5b, 5c via the above stub-bus 7a, 7b, 7c from an accessed DRAM 3a, 3b, 3c are relayed (where appropriate, in converted form) via a respective north bound channel of one of the buses 6a, 6b, 6c to the previous buffer component in the daisy chain (or—by the buffer component 5a of the first the FBDIMM 2a—to the memory controller 4).
As is illustrated in FIG. 1, the stub-buses 7a, 7b, 7c on the FBDIMMs 2a, 2b, 2c, and the north bound channels of the buses 6a, 6b, 6c may e.g., comprise a data bandwidth of 144 bits per DRAM clock period, and the south bound channels of the buses 6a, 6b, 6c e.g., a data bandwidth of only 72 bits per DRAM clock period, leading to a 1:2 write to read ratio, reflecting statistics in typical memory access patterns.
However, in a system corresponding to the memory system 1 illustrated in FIG. 1, a faster memory controller 4, faster buses 6a, 6b, 6c and 7a, 7b, 7c, and faster buffer components 5a, 5b, 5c still might not lead to an increased overall performance.
For these or other reasons, there is a need for the present invention.